Wafer-level packaging of semiconductor devices is a relatively new but widely used technology that allows semi-conductor and MEMS devices to be packaged on a wafer scale with solder balls attached directly to the die (typically through a stress-relief layer). This technology yields the smallest possible package size for any given device while at the same time reducing packaging cost by packaging an entire wafer of die in a batch process. The most common wafer-level packaging technologies (ex. Shellcase, uBGA, WAVE, and others) typically make direct contact to the CMOS wafer metallization, but cannot easily contact the top-layer of the MEMS since it is typically electrically isolated from the CMOS. In cases where the MEMS handle or cap wafer or a metal layer deposited onto the MEMS handle or cap wafer must be electrically contacted, the current wafer-level packaging technologies cannot be directly applied.
Accordingly, what is desired is a system and method which would overcome the above-identified issues. The method and system should be easy to implement, cost-effective, and adaptable to existing systems. The present invention addresses such a need.